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openrisc

Here are 23 public repositories matching this topic...

larsbrinkhoff / awesome-cpus

All CPU and MCU documentation in one place

avr arm cpu z80 mcu pdp-10 sparc m68k xtensa powerpc risc-v pdp-11 openrisc pdp-8 pdp-1 datasheet vax microblaze i860 i960

UpdatedNov 4, 2022
HTML

s-macke / jor1k

Online OR1K Emulator running Linux

javascript linux emulator openrisc

UpdatedJul 27, 2022
JavaScript

openrisc / mor1kx

mor1kx - an OpenRISC 1000 processor IP core

verilog openrisc

UpdatedMar 29, 2025
Verilog

optimsoc / optimsoc

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

hardware openrisc noc fossi

UpdatedMar 8, 2021
C

SweetAda

gabriele-galeotti / SweetAda

Ada-language framework

avr arm embedded mips x86-64 x86 ada sparc m68k powerpc risc-v openrisc microblaze nios2 embedded-system sh4 ada-language s390 neorv32 gnat-ada

UpdatedMay 8, 2025
Ada

kuopinghsu / callgraph-gen

Generating the call graph from elf binary file

arm riscv callgraph callstack xtensa graphviz-dot openrisc vcg calltree

UpdatedMay 3, 2023
Assembly

MPSoC-DV

PacoReinaCampo / MPSoC-DV

Multi-Processor System on Chip verified with UVM/OSVVM/FV

uvm formal-verification osvvm risc-v mpsoc openrisc msp340

UpdatedMay 5, 2025
SystemVerilog

SoC-DV

PacoReinaCampo / SoC-DV

System on Chip verified with UVM/OSVVM/FV

soc uvm formal-verification osvvm risc-v openrisc msp340

UpdatedMay 6, 2025
SystemVerilog

ilyakurdyukov / ida-openrisc

OpenRISC 1000 processor module for IDA 7.x

ida idapython or1k openrisc

UpdatedFeb 13, 2024
Python

janweinstock / or1kiss

An OpenRISC 1000 Instruction Set Simulator

simulator iss openrisc

UpdatedMar 25, 2025
C++

bandvig / or1k_marocchino

OpenRISC processor IP core based on Tomasulo algorithm

verilog openrisc

UpdatedFeb 18, 2022
Verilog

andrakis / Elispidae

Lisp-based stackless interpreter and platform, including microthreading. Features taken from Lisp and Erlang.

lambda visual-studio interpreter makefile x86-64 stackless cplusplus-14 linux-app or1k lithp openrisc

UpdatedAug 5, 2019
C++

PU-DV

PacoReinaCampo / PU-DV

Processing Unit verified with UVM/OSVVM/FV

uvm formal-verification osvvm risc-v openrisc pu msp340

UpdatedMay 6, 2025
SystemVerilog

timvideos / qemu-litex

fpga qemu fpga-soc-linux or1k fpga-soc openrisc litex misoc migen liteeth

UpdatedSep 13, 2018
C

snps-virtualprototyping / ocx-or1kiss

OpenCpuX wrapper for the or1kiss OpenRISC ISS

openrisc opencpux virtual-prototyping

UpdatedNov 13, 2019
C++

PU-OR1K

PacoReinaCampo / PU-OR1K

Processing Unit with OpenRISC-32 / OpenRISC-64

openrisc 32-bit pu harvard-architecture

UpdatedMay 8, 2025
SystemVerilog

MPSoC-OR1K

PacoReinaCampo / MPSoC-OR1K

Multi-Processor System on Chip with OpenRISC-32 / OpenRISC-64

mpsoc openrisc mimd

UpdatedMay 8, 2025
SystemVerilog

lucasasselli / or1200-onchip-obfuscator

This project is a modified verison of the OpenRISC 1200 open-source processor, designed to estimate the feasibility of using an On-Chip Software Obfuscator to reduce the controllability over software activated Hardware Trojans.

openrisc hardware-security hardware-trojans

UpdatedApr 11, 2021
Verilog

SoC-OR1K

PacoReinaCampo / SoC-OR1K

System on Chip with OpenRISC-32 / OpenRISC-64

simd soc openrisc misd

UpdatedMay 8, 2025
SystemVerilog

seyang1 / pub-ips

processor-architecture asic processor riscv gpgpu verilog gpu-computing systemverilog verilog-hdl openrisc verilog-components systemverilog-hdl gpgpu-computing verilog-project processor-design verilog-code asic-design

UpdatedOct 18, 2022

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